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LTC1852/LTC1853 8-Channel, 10-Bit/12-Bit, 400ksps, Low Power, Sampling ADCs FEATURES
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DESCRIPTION
The 10-bit LTC(R)1852 and 12-bit LTC1853 are complete 8-channel data acquisition systems. They include a flexible 8-channel multiplexer, a 400ksps successive approximation analog-to-digital converter, an internal reference and a parallel output interface. The multiplexer can be configured for single-ended or differential inputs, two gain ranges and unipolar or bipolar operation. The ADCs have a scan mode that will repeatedly cycle through all 8 multiplexer channels and can also be programmed to sequence through up to 16 addresses and configurations. The sequence can also be read back from internal memory. The reference and buffer amplifier provide pin strappable ranges of 4.096V, 2.5V and 2.048V. The parallel output includes the 10-bit or 12-bit conversion result plus the 4-bit multiplexer address. The digital outputs are powered from a separate supply allowing for easy interface to 3V digital logic. Typical power consumption is 10mW at 400ksps from a single 5V supply and 3mW at 250ksps from a single 3V supply.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
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Flexible 8-Channel Multiplexer Single-Ended or Differential Inputs Two Gain Ranges Unipolar or Bipolar Operation Scan Mode and Programmable Sequencer Eliminate Configuration Software Overhead Low Power: 3mW at 250ksps 2.7V to 5.5V Supply Range Internal or External Reference Operation Parallel Output Includes MUX Address Nap and Sleep Shutdown Modes Pin Compatible up-grade 1.25Msps 10-Bit LTC1850 and 12-Bit LTC1851
APPLICATIONS
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High Speed Data Acquisition Test and Measurement Imaging Systems Telecommunications Industrial Process Control Spectrum Analysis
BLOCK DIAGRAM
LTC1853 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 2.5V REFERENCE 8-CHANNEL MULTIPLEXER INTERNAL CLOCK CONTROL LOGIC AND PROGRAMMABLE SEQUENCER M1 SHDN CS CONVST RD WR DIFF A2 A1 A0 UNI/BIP PGA M0 OVDD BUSY DIFFOUT/S6 A2OUT/S5 A1OUT/S4 A0OUT/S3 D11/S2 D10/S1 D9/S0 D8 D7 D6 D5 D4 D3 D2 D1 D0 OGND
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Integral Linearity
1.0
0.5
INL ERROR (LSBs)
0
-0.5
REFOUT
+ -
12-BIT SAMPLING ADC
DATA LATCHES
OUTPUT DRIVERS
-1.0
0
REFIN
REF AMP
512 1024 1536 2048 2560 3072 3584 4096 CODE 1852 F01
REFCOMP
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LTC1852/LTC1853 ABSOLUTE MAXIMUM RATINGS
OVDD = VDD (Note 1, 2)
Supply Voltage (VDD) ..................................................6V Analog Input Voltage (Note 3) ..... - 0.3V to (VDD + 0.3V) Digital Input Voltage (Note 4) .................... -0.3V to 10V Digital Output Voltage ..................-0.3V to (VDD + 0.3V) Power Dissipation ...............................................500mW
Ambient Operating Temperature Range LTC1852C/LTC1853C .............................. 0C to 70C LTC1852I/LTC1853I............................. -40C to 85C Storage Temperature Range...................-65C to 150C Lead Temperature (Soldering, 10 sec) ................. 300C
PIN CONFIGURATION
LTC1852
TOP VIEW CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 1 2 3 4 5 6 7 8 9 48 M1 47 SHDN 46 CS 45 CONVST 44 RD 43 WR 42 DIFF 41 A2 40 A1 39 A0 38 UNI/BIP 37 PGA 36 M0 35 OVDD 34 OGND 33 BUSY 32 NC 31 NC 30 D0 29 D1 28 D2 27 D3 26 D4 25 D5 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM 1 2 3 4 5 6 7 8 9
LTC1853
TOP VIEW 48 M1 47 SHDN 46 CS 45 CONVST 44 RD 43 WR 42 DIFF 41 A2 40 A1 39 A0 38 UNI/BIP 37 PGA 36 M0 35 OVDD 34 OGND 33 BUSY 32 D0 31 D1 30 D2 29 D3 28 D4 27 D5 26 D6 25 D7
REFOUT 10 REFIN 11 REFCOMP 12 GND 13 VDD 14 VDD 15 GND 16 DIFFOUT/S6 17 A2OUT/S5 18 A1OUT/S4 19 A0OUT/S3 20 D9/S2 21 D8/S1 22 D7/S0 23 D6 24
REFOUT 10 REFIN 11 REFCOMP 12 GND 13 VDD 14 VDD 15 GND 16 DIFFOUT/S6 17 A2OUT/S5 18 A1OUT/S4 19 A0OUT/S3 20 D11/S2 21 D10/S1 22 D9/S0 23 D8 24
FW PACKAGE 48-LEAD PLASTIC TSSOP
FW PACKAGE 48-LEAD PLASTIC TSSOP
TJMAX = 150C, JA = 110C/W
TJMAX = 150C, JA = 110C/W
ORDER INFORMATION
LEAD FREE FINISH LTC1852CFW#PBF LTC1852IFW#PBF LTC1853CFW#PBF LTC1853IFW#PBF TAPE AND REEL LTC1852CFW#TRPBF LTC1852IFW#TRPBF LTC1853CFW#TRPBF LTC1853IFW#TRPBF PART MARKING LTC1852CFW LTC1852IFW LTC1853CFW LTC1853IFW PACKAGE DESCRIPTION 48-Lead Plastic TSSOP (6.1mm) 48-Lead Plastic TSSOP (6.1mm) 48-Lead Plastic TSSOP (6.1mm) 48-Lead Plastic TSSOP (6.1mm) TEMPERATURE RANGE 0C to 70C -40C to 85C 0C to 70C -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
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LTC1852/LTC1853
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 2.7V to 5.5V, REFCOMP < VDD (Notes 5,6)
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error (Bipolar and Unipolar) Gain = 1 (PGA = 1) Gain = 2 (PGA = 0) Offset Error Match (Bipolar and Unipolar) Unipolar Gain Error Gain = 1 (PGA = 1) Gain = 2 (PGA = 0) Unipolar Gain Error Match Bipolar Gain Error Gain = 1 (PGA = 1) Gain = 2 (PGA = 0) Bipolar Gain Error Match Unipolar Gain Error Gain = 1 (PGA = 1) Gain = 2 (PGA = 0) Bipolar Gain Error Gain = 1 (PGA = 1) Gain = 2 (PGA = 0) Full-Scale Error Temperature Coefficient With External 2.5V Reference Applied to REFCOMP VDD = 2.7V to 5.5V, fS 250kHz With External 2.5V Reference Applied to REFCOMP VDD = 2.7V to 5.5V, fS 250kHz
l l l l
CONVERTER CHARACTERISTICS
CONDITIONS
MIN
l
LTC1852 TYP 0.25 0.25 0.5 1
MAX 1 1 2 4 0.5
MIN 12
LTC1853 TYP 0.35 0.25 1 2
MAX 1 1 6 12 1 4 8 1 4 8 1
UNITS Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB ppm/C
10
(Note 7) (Note 8) REFCOMP 2V
l l l l
With External 4.096V Reference Applied to REFCOMP (Note 12) VDD = 4.75V to 5.25V, fS 400kHz With External 4.096V Reference Applied to REFCOMP (Note 12) VDD = 4.75V to 5.25V, fS 400kHz
2 4 0.5 2 4 0.5 1 2 1 2 15 3 6 3 6 1.5 3 1.5 3 15
8 16 8 16
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Notes 5)
SYMBOL VIN PARAMETER Analog Input Range (Note 9) Unipolar, Gain = 1 (PGA = 1) Unipolar, Gain = 2 (PGA = 0) Bipolar, Gain = 1 (PGA = 1) Bipolar, Gain = 2 (PGA = 0) Analog Input Leakage Current Analog Input Capacitance Between Conversions (Gain = 1) Between Conversions (Gain = 2) During Conversions CONDITIONS 2.7V VDD 5.5V, REFCOMP VDD 0 - REFCOMP 0 - REFCOMP/2 REFCOMP/2 REFCOMP/4
l
ANALOG INPUT
MIN
TYP
MAX
UNITS V V V V
IIN CIN
1 15 25 5 50 50 150 150
A pF pF pF ns ns ns psRMS dB
tACQ tS(MUX) tAP tjitter CMRR
Sample-and-Hold Acquisition Time Multiplexer Settling Time (Includes tACQ) Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio VDD = 5V VDD = 5V
- 0.5 2 60
DYNAMIC ACCURACY
SYMBOL S/(N + D) THD SFDR PARAMETER Total Harmonic Distortion Spurious Free Dynamic Range
TA = 25C. (Notes 5)
CONDITIONS 40kHz Input Signal 40kHz Input Signal, First 5 Harmonics 40kHz Input Signal MIN TYP 72.5 -80 -85 MAX UNITS dB dB dB
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Signal-to-Noise Plus Distortion Ratio
3
LTC1852/LTC1853 INTERNAL REFERENCE
PARAMETER REFOUT Output Voltage REFOUT Output Temperature Coefficient REFOUT Line Regulation Reference Buffer Gain REFCOMP Output Voltage REFCOMP Impedance External 2.5V Reference (VDD = 5V) Internal 2.5V Reference (VDD = 5V) Impedance to GND, REFIN = VDD
TA = 25C. (Notes 5, 6)
CONDITIONS IOUT = 0 IOUT = 0 2.7 VDD 5.5, IOUT = 0 1.6368 4.092 4.060 MIN 2.48 TYP 2.50 15 0.01 1.6384 4.096 4.096 19.2 1.6400 4.100 4.132 MAX 2.52 UNITS V ppm/C LSB/V V/V V V k
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 5V (Note 5)
SYMBOL VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage VDD = 4.75V, IO = -10A VDD = 4.75V, IO = - 200A VDD = 4.75V, IO = 160A VDD = 4.75V, IO = 1.6mA CS High (Note 9) VOUT = 0V VOUT = VDD

DIGITAL INPUTS AND DIGITAL OUTPUTS
CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD
MIN

TYP
MAX 0.8 5
UNITS V V A pF V V
2.4
1.5 4.5 4 0.5 0.10 0.4 10 15 -20 30
V V A pF mA mA
Hi-Z Output Leakage D11 to D0, A0, A1, A2OUT, DIFFOUT VOUT = 0V to VDD, CS High Hi-Z Capacitance D11 to D0 Output Source Current Output Sink Current
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VDD = 5V (Note 5)
SYMBOL VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage VDD = 2.7V, IO = -10A VDD = 2.7V, IO = - 200A VDD = 2.7V, IO = 160A VDD = 2.7V, IO = 1.6mA CS High (Note 9) VOUT = 0V VOUT = VDD

DIGITAL INPUTS AND DIGITAL OUTPUTS
CONDITIONS VDD = 3.3V VDD = 2.7V VIN = 0V to VDD
MIN

TYP
MAX 0.45 5
UNITS V V A pF V V
1.9
1.5 2.5 2 0.05 0.10 0.4 10 15 -10 15
V V A pF mA mA
Hi-Z Output Leakage D11 to D0, A0, A1, A2OUT, DIFFOUT VOUT = 0V to VDD, CS High Hi-Z Capacitance D11 to D0 Output Source Current Output Sink Current
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LTC1852/LTC1853 POWER REQUIREMENTS
SYMBOL VDD OVDD IDD PDISS IDDPD PARAMETER Analog Positive Supply Voltage Output Positive Supply Voltage Positive Supply Current Power Dissipation Power Down Positive Supply Current Nap Mode Sleep Mode Power Down Power Dissipation Nap Mode Sleep Mode Power Down Power Dissipation Nap Mode Sleep Mode
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS (Note 10) (Note 10) VDD = OVDD = 5V, fS = 400kHz VDD = OVDD = 2.7V, fS = 250kHz VDD = OVDD = 5V, fS = 400kHz VDD = OVDD = 2.7V, fS = 250kHz SHDN = Low, CS = Low SHDN = Low, CS = High VDD = VDD = OVDD = 5V, fS = 400kHz SHDN = Low, CS = Low SHDN = Low, CS = High VDD = VDD = OVDD = 3V, fS = 250kHz SHDN = Low, CS = Low SHDN = Low, CS = High

MIN 2.7 2.7
TYP
MAX 5.5 5.5
UNITS V V mA mA mW mW mA A mW mW mW mW
2 0.83 10 2.25 0.5 20 2.5 0.1 1.5 0.06
3 1.33 15 4
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
SYMBOL fSAMPLE(MAX) PARAMETER Maximum Sampling Frequency Acquisition + Conversion tCONV tACQ t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Conversion Time Acquisition Time CS to RD Setup Time CS to CONVST Setup Time CS to SHDN Setup Time SHDN to CONVST Wake-Up Time CONVST Low Time CONVST to BUSY Delay Data Ready Before BUSY
TIMING CHARACTERISTICS
CONDITIONS VDD = 5.5V VDD = 2.7V VDD = 5.5V VDD = 2.7V VDD = 5.5V VDD = 2.7V (Note 13) (Notes 9, 10) (Notes 9, 10) (Notes 9, 10) Nap Mode (Note 10) Sleep Mode (Note 10) (Notes 10, 11) CL = 25pF

MIN 400 250
TYP
MAX
UNITS kHz kHz
2.5 4.0 2.0 3.5 150 0 10 200 200 10 50 10 60 20 15 50 -5 20 35 45 45 60 30 35 40 35
s s s s ns ns ns ns ns ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Delay Between Conversions Wait Time RD After BUSY Data Access Time After RD
(Note 10)

CL = 25pF CL = 100pF
25
t11
BUS Relinquish Time 0C to 70C - 40C to 85C

10
t12
RD Low Time
t10
5
LTC1852/LTC1853 TIMING CHARACTERISTICS
SYMBOL t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 PARAMETER CONVST High Time Latch Setup Time Latch Hold Time WR Low Time WR High Time M1 to M0 Setup Time M0 to BUSY Delay M0 to WR (or RD) Setup Time M0 High Pulse Width RD High Time Between Readback Reads Last WR (or RD) to M0 M0 to RD Setup Time M0 to CONVST Aperture Delay Aperture Jitter
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5)
CONDITIONS (Note 10) (Note 10) (Notes 9, 10) (Note 10) (Note 10) (Notes 9, 10) M1 High (Notes 9, 10) (Note 10) (Note 10) (Note 10) (Notes 9, 10) (Note 10)

MIN 50 10 10 50 50 10
TYP
MAX
UNITS ns ns ns ns ns ns
20 t19 50 50 10 t19 t19 - 0.5 2
ns ns ns ns ns ns ns ns psRMS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with OGND and GND wired together unless otherwise noted. Note 3: When these pin voltages are taken below ground or above VDD, they will be clamped by internal diodes. This product can handle input currents of 100mA below ground or above VDD without latchup. Note 4: When these pin voltages are taken below ground, they will be clamped by internal diodes. This product can handle input currents of 100mA below ground without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, fSAMPLE = 400kHz, tr = tf = 2ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a singleended input on any channel with COM grounded. Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual end points of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from - 0.5LSB when the output code flickers between 1111 1111 1111 and 0000 0000 0000. For the LTC1853 and between 11 1111 1111 and 00 0000 0000 for the LTC1852. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: The falling CONVST edge starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For the best results, ensure that CONVST returns high either within 400ns after the start of the conversion or after BUSY rises. Note 12: The analog input range is determined by the voltage on REFCOMP The gain error specification is tested with an external 4.096V . but is valid for any value of REFCOMP greater than 2V and less than (VDD - 0.5V.) Note 13: MUX address is updated immediately after BUSY falls.
TYPICAL PERFORMANCE CHARACTERISTICS
Differential Linearity
1.0
0 -20
8192 Point FFT with fIN = 39.599kHz
0.5
DNL ERROR (LBS)
AMPLITUDE (dB)
-40 -60 -80 -100
0
-0.5
-1.0
-120
0 CODE 4096
1852 F02
0 FREQUENCY (kHz)
200
1852 F03
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LTC1852/LTC1853 PIN FUNCTIONS
CH0 to CH7 (Pins 1 to 8): Analog Input Pins. Input pins can be used single ended relative to the analog input common pin or differentially in pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7). COM (Pin 9): Analog Input Common Pin. For single-ended operation (DIFF = 0), COM is the "-" analog input. COM is disabled when DIFF is high. REFOUT (Pin 10): Internal 2.5V Reference Output. Bypass to analog ground plane with 1F . REFIN (Pin 11): Reference Mode Select/Reference Buffer Input. REFIN selects the reference mode and acts as the reference buffer input. REFIN tied to ground (Logic 0) will produce 2.048V on the REFCOMP pin. REFIN tied to the positive supply (Logic 1) disables the reference buffer to allow REFCOMP to be driven externally. For voltages between 1V and 2.6V, the reference buffer produces an output voltage on the REFCOMP pin equal to 1.6384 times the voltage on REFIN (4.096V on REFCOMP for a 2.5V input on REFIN). REFCOMP (Pin 12): Reference Buffer Output. REFCOMP sets the full-scale input span. The reference buffer produces an output voltage on the REFCOMP pin equal to 1.6384 times the voltage on the REFIN pin (4.096V on REFCOMP for a 2.5V input on REFIN). REFIN tied to ground will produce 2.048V on the REFCOMP pin. REFCOMP can be driven externally if REFIN is tied to the positive supply. Bypass to analog ground plane with 10F tantalum in parallel with 0.1F ceramic or 10F ceramic. GND (Pins 13, 16): Ground. Tie to analog ground plane. VDD (Pins 14, 15): Positive Supply. Bypass to analog ground plane with 10F tantalum in parallel with 0.1F ceramic or 10F ceramic. DIFFOUT/S6 (Pin 17): Three-State Digital Data Output. Active when RD is low. Following a conversion, the single-ended/differential bit of the present conversion is available on this pin concurrent with the conversion result. In Readback mode, the single-ended/differential bit of the current sequencer location (S6) is available on this pin. The output swings between OVDD and OGND. A2OUT/S5, A1OUT/S4, A0OUT/S3 (Pins 18 to 20): ThreeState Digital MUX Address Outputs. Active when RD is low. Following a conversion, the MUX address of the present conversion is available on these pins concurrent with the conversion result. In Readback mode, the MUX address of the current sequencer location (S5-S3) is available on these pins. The outputs swing between OVDD and OGND. D9/S2 (Pin 21, LTC1852): Three-State Digital Data Output. Active when RD is low. Following a conversion, bit 9 of the present conversion is available on this pin. In Readback mode, the unipolar/bipolar bit of the current sequencer location (S2) is available on this pin. The output swings between OVDD and OGND. D11/S2 (Pin 21, LTC1853): Three-State Digital Data Output. Active when RD is low. Following a conversion, bit 11 of the present conversion is available on this pin. In Readback mode, the unipolar/bipolar bit of the current sequencer location (S2) is available on this pin. The output swings between OVDD and OGND. D8/S1 (Pin 22, LTC1852): Three-State Digital Data Outputs. Active when RD is low. Following a conversion, bit 8 of the present conversion is available on this pin. In Readback mode, the gain bit of the current sequencer location (S1) is available on this pin. The output swings between OVDD and OGND. D10/S1 (Pin 22, LTC1853): Three-State Digital Data Outputs. Active when RD is low. Following a conversion, bit 10 of the present conversion is available on this pin. In Readback mode, the gain bit of the current sequencer location (S1) is available on this pin. The output swings between OVDD and OGND. D7/S0 (Pin 23, LTC1852): Three-State Digital Data Outputs. Active when RD is low. Following a conversion, bit 7 of the present conversion is available on this pin. In Readback mode, the end of sequence bit of the current sequencer location (S0) is available on this pin. The output swings between OVDD and OGND.
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LTC1852/LTC1853 PIN FUNCTIONS
D9/S0 (Pin 23, LTC1853): Three-State Digital Data Outputs. Active when RD is low. Following a conversion, bit 9 of the present conversion is available on this pin. In Readback mode, the end of sequence bit of the current sequencer location (S0) is available on this pin. The output swings between OVDD and OGND. D6 to D0 (Pins 24 to 30, LTC1852): Three-State Digital Data Outputs. Active when RD is low. The outputs swing between OVDD and OGND. D8 to D0 (Pins 24 to 32, LTC1853): Three-State Digital Data Outputs. Active when RD is low. The outputs swing between OVDD and OGND. NC (Pins 31 to 32, LTC1852): No Connect. There is no internal connection to these pins. BUSY (Pin 33): Converter Busy Output. The BUSY output has two functions. At the start of a conversion, BUSY will go low and remain low until the conversion is completed. The rising edge may be used to latch the output data. BUSY will also go low while the part is in Program/Readback mode (M1 high, M0 low) and remain low until M0 is brought back high. The output swings between OVDD and OGND. OGND (Pin 34): Digital Data Output Ground. Tie to analog ground plane. May be tied to logic ground if desired. OVDD (Pin 35): Digital Data Output Supply. Normally tied to 5V, can be used to interface with 3V digital logic. Bypass to OGND with 10F tantalum in parallel with 0.1F ceramic or 10F ceramic. M0 (Pin 36): Mode Select Pin 0. Used in conjunction with M1 to select operating mode. See Table 5. PGA (Pin 37): Gain Select Input. A high logic level selects gain = 1, a low logic level selects gain = 2. UNI/BIP (Pin 38): Unipolar/Bipolar Select Input. Logic low selects a unipolar input span, a high logic level selects a bipolar input span. A0 to A2 (Pins 39 to 41): MUX Address Input Pins. DIFF (Pin 42): Single-Ended/Differential Select Input. A low logic level selects single ended, a high logic level selects differential. WR (Pin 43): Write Input. In Direct Address mode, WR low enables the MUX address and configuration input pins (Pins 37 to 42). WR can be tied low or the rising edge of WR can be used to latch the data. In Program mode, WR is used to program the sequencer. WR low enables the MUX address and configuration input pins (Pins 37 to 42). The rising edge of WR latches the data and increments the counter to the next sequencer location. RD (Pin 44): Read Input. During normal operation, RD enables the output drivers when CS is low. In Readback mode (M1 high, M0 low), RD going low reads the current sequencer location, RD high advances to the next sequencer location. CONVST (Pin 45): Conversion Start Input. This active low signal starts a conversion on its falling edge. CS (Pin 46): Chip Select Input. The chip select input must be low for the ADC to recognize the CONVST and RD inputs. If SHDN is low, a low logic level on CS selects Nap mode; a high logic level on CS selects Sleep mode. SHDN (Pin 47): Power Shutdown Input. A low logic level will invoke the Shutdown mode selected by the CS pin. CS low selects Nap mode, CS high selects Sleep mode. Tie high if unused. M1 (Pin 48): Mode Select Pin 1. Used in conjunction with M0 to select operating mode. See Table 5.
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LTC1852/LTC1853 PIN FUNCTIONS
PIN 1 to 8 9 10 11 12 13 14 15 16 17 18 19 20 21 21 22 22 23 23 24 to 30 24 to 32 31 to 32 33 34 35 36 37 38 39 to 41 42 43 44 45 46 47 48 NAME CH0 to CH7 COM REFOUT REFIN REFCOMP GND VDD VDD GND DIFFOUT/S6 A2OUT/S5 A1OUT/S4 A0OUT/S3 D9/S2 (LTC1852) D11/S2 (LTC1853) D8/S1 (LTC1852) D10/S1 (LTC1853) D7/S0 (LTC1852) D9/S0 (LTC1853) D6 to D0 (LTC1852) D8 to D0 (LTC1853) NC (LTC1852) BUSY OGND OVDD M0 PGA UNI/BIP A0 to A2 DIFF WR RD CONVST CS SHDN M1 DESCRIPTION Analog Inputs Analog Input Common Pin 2.5V Reference Output Reference Buffer Input Reference Buffer Output Ground Positive Supply Positive Supply Ground Single-Ended/Differential Output MUX Address Output MUX Address Output MUX Address Output Data Output Data Output Data Output Data Output Data Output Data Output Data Outputs Data Outputs No Connect Converter Busy Output Output Ground Output Supply Mode Select Pin 0 Gain Select Input Unipolar/Bipolar Input MUX Address Inputs Single-Ended/Differential Input Write Input, Active Low Read Input, Active Low Conversion Start Input, Active Low Chip Select Input, Active Low Shutdown Input, Active Low Mode Select Pin 1 2.7 0 0 0 0 0 0 0 0 0 0 0 OGND 0 5 5.5 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD 0VDD -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 VDD + 0.3 VDD + 0.3 6 6 6 6 6 6 6 6 6 6 6 6 OGND OGND OGND OGND OGND OGND OGND OGND OGND OGND OGND OGND 2.7 2.7 0 MIN 0 0 2.5 2.5 4.096 0 5 5 0 0VDD 0VDD 0VDD 0VDD 0VDD 0VDD 0VDD 0VDD 0VDD 0VDD 0VDD 0VDD 5.5 5.5 VDD NOMINAL (V) TYP MAX VDD VDD ABSOLUTE MAXIMUM (M) MIN MAX -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 6 6 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3
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LTC1852/LTC1853 APPLICATIONS INFORMATION
The LTC1852/LTC1853 are complete and very flexible data acquisition systems. They consist of a 10-bit/12-bit, 400ksps capacitive successive approximation A/D converter with a wideband sample-and-hold, a configurable 8-channel analog input multiplexer, an internal reference and reference buffer amplifier, a 16-bit parallel digital output and digital control logic, including a programmable sequencer. CONVERSION DETAILS The core analog-to-digital converter in the LTC1852/ LTC1853 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 10-bit/12-bit parallel output. Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion, the successive approximation register (SAR) is reset. Once a conversion cycle is begun, it cannot be restarted. During the conversion, the internal differential capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). The outputs of the analog input multiplexer are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum delay of 150ns will provide enough time for the sample-and-hold capacitors to acquire the analog signal. During the convert phase, the comparator zeroing switches are open, putting the comparator into compare mode. The input switches connect CSAMPLE to ground, transferring the differential analog input charge onto the summing junction. This input charge is successively compared with the binary weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of the conversion, the differential DAC output balances the input charges. The SAR contents (a 10-bit/12-bit data word), which represents the difference of the analog input multiplexer outputs, and the 4-bit address word are loaded into the 14-bit/16-bit output latches. DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the ADC output. The output is band limited to frequencies above DC to below half the sampling frequency. The effective number of bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: ENOB = [S/(N + D) - 1.76]/6.02 where ENOB is the effective number of bits and S/(N + D) is expressed in dB. At the maximum sampling rate of 400kHz, the LTC1852/LTC1853 maintain near ideal ENOBs up to and beyond the Nyquist input frequency of 200kHz. Total Harmonic Distortion Total harmonic distortion is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: THD= 20Log V22 + V32 + V42 +...Vn2 V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. The LTC1852/LTC1853 have good distortion performance up to the Nyquist frequency and beyond. Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency.
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LTC1852/LTC1853 APPLICATIONS INFORMATION
If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: IMD ( fa fb) = 20Log Amplitude at ( fa fb) Amplitude at fa inputs as shown in Table 1. Unused inputs (including the COM in the differential case) should be grounded to prevent noise coupling.
Table 1. Multiplexer Address Table
MUX ADDRESS DIFF A2 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 + + + + + + + + DIFFERENTIAL CHANNEL SELECTION + - - + + - - + + - - + + - - + * * * * * * * * SINGLE-ENDED CHANNEL SELECTION - - - - - - - - A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. Full-Power and Full-Linear Bandwidth The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal. The full-linear bandwidth is the input frequency at which the S/(N + D) has dropped to 68dB for the LTC1853 (11 effective bits) or 56dB for the LTC1852 (9 effective bits). The LTC1852/LTC1853 have been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter's Nyquist frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. ANALOG INPUT MULTIPLEXER The analog input multiplexer is controlled using the single-ended/differential pin (DIFF), three MUX address pins (A2, A1, A0), the unipolar/bipolar pin (UNI/BIP) and the gain select pin (PGA). The single-ended/differential pin (DIFF) allows the user to configure the MUX as eight single-ended channels relative to the analog input common pin (COM) when DIFF is low or as four differential pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7) when DIFF is high. The channels (and polarity in the differential case) are selected using the MUX address
MUX ADDRESS DIFF A2 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
A0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
*Not used in differential mode. Connect to AGND.
In addition to selecting the MUX channel, the LTC1852/ LTC1853 also allows the user to select between two gains and unipolar or bipolar inputs for a total of four input spans. PGA high selects a gain of 1 (the input span is equal to the voltage on REFCOMP). PGA low selects a gain of 2 where the input span is equal to half of the voltage on REFCOMP . UNI/BIP low selects a unipolar input span, UNI/BIP high selects a bipolar input span. Table 2 summarizes the possible input spans.
Table 2. Input Span Table
INPUT SPAN UNI/BIP 0 0 1 1 PGA 0 1 0 1 0 - REFCOMP/2 0 - REFCOMP REFCOMP/4 REFCOMP/2 REFCOMP = 4.096V 0 - 2.048V 0 - 4.096V 1.024V 2.048V
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LTC1852/LTC1853 APPLICATIONS INFORMATION
The LTC1852/LTC1853 have a unique differential sampleand-hold circuit that allows rail-to-rail inputs. The ADC will always convert the difference of the "+" and "-" inputs independent of the common mode voltage. The common mode rejection holds up to high frequencies. The only requirement is that both inputs can not exceed the AVDD power supply voltage or ground. When a bipolar input span is selected the "+" input can swing full scale relative to the "-" input but neither input can exceed AVDD or go below ground. Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are independent of the common mode voltage, however, the bipolar offset will vary. The change in bipolar offset is typically less than 0.1% of the common mode voltage. Some AC applications may have their performance limited by distortion. Most circuits exhibit higher distortion when signals approach the supply or ground. THD will degrade as the inputs approach either power supply rail. Distortion can be reduced by reducing the signal amplitude and keeping the common mode voltage at approximately midsupply. Driving the Analog Inputs The inputs of the LTC1852/LTC1853 are easy to drive. Each of the analog inputs can be used as a single-ended input relative to the input common pin (CH0-COM, CH1-COM, etc.) or in pairs (CH0 and CH1, CH2 and CH3, CH4 and CH5, CH6 and CH7) for differential inputs. Regardless of the MUX configuration, the "+" and "-" inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC1852/LTC1853 inputs can be driven directly. As source impedance increases, so will acquisition time. For minimum acquisition time with high source impedance, a buffer amplifier should be used. The only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be less than 150ns for full throughput rate). Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (<100) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of +1 and has a unity-gain bandwidth of 50MHz, then the output impedance at 50MHz should be less than 100. The second requirement is that the closed-loop bandwidth must be greater than 10MHz to ensure adequate smallsignal settling for full throughput rate. The following list is a summary of the op amps that are suitable for driving the LTC1852/LTC1853, more detailed information is available in the Linear Technology Databooks, the LinearViewTM CD-ROM and on our web site at www.linear-tech.com. LT(R)1360: 50MHz Voltage Feedback Amplifier. 2.5V to 15V supplies. 5mA supply current. Low distortion. LT1363: 70MHz Voltage Feedback Amplifier. 2.5V to 15V supplies. 7.5mA supply current. Low distortion. LT1364/LT1365: Dual and Quad 70MHz Voltage Feedback Amplifiers. 2.5V to 15V supplies. 7.5mA supply current per amplifier. Low distortion. LT1468/LT1469: Single and Dual 90MHz Voltage Feedback Amplifier. 5V to 15V supplies. 7mA supply current per amplifier. Lowest noise and low distortion. LT1630/LT1631: Dual and Quad 30MHz Rail-to-Rail Voltage Feedback Amplifiers. Single 3V to 15V supplies. 3.5mA supply current per amplifier. Low noise and low distortion. LT1632/LT1633: Dual and Quad 45MHz Rail-to-Rail Voltage Feedback Amplifiers. Single 3V to 15V supplies. 4.3mA supply current per amplifier. Low distortion. LT1806/LT1807: Single and Dual 325MHz Rail-to-Rail Voltage Feedback Amplifier. Single 3V to 5V supplies. 13mA supply current. Lowest distortion.
LinearView is a trademark of Linear Technology Corporation.
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LTC1852/LTC1853 APPLICATIONS INFORMATION
LT1809/LT1810: Single and Dual 180MHz Rail-to-Rail Voltage Feedback Amplifier. Single 3V to 15V supplies. 20mA supply current. Lowest distortion. LT1812/LT1813: Single and Dual 100MHz Voltage Feedback Amplifier. Single 5V to 5V supplies. 3.6mA supply current. Low noise and low distortion. Input Filtering The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1852/LTC1853 noise and distortion. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For instance, a 200 source resistor and a 1000pF capacitor to ground on the input will limit the input bandwidth to 800kHz.The capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. REFERENCE The LTC1852/LTC1853 includes an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500V and has a very flexible 3-pin interface. REFOUT is the 2.5V bandgap output, REFIN is the input to the reference buffer and REFCOMP is the reference buffer output. The input span is determined by the voltage appearing on the REFCOMP pin as shown in Table 2. The reference buffer has a gain of 1.6384 and is factory trimmed by forcing an external 2.500V on the REFIN pin and trimming REFCOMP to 4.096V. The 3-pin interface allows for three pin-strappable Reference modes as well as two additional external Reference modes. For voltages on the REFIN pin ranging from 1V to 2.6V, the output voltage on REFCOMP will equal 1.6384 times the voltage on the REFIN pin. In this mode, the REFIN pin can be tied to REFOUT to use the internal 2.5V reference to get 4.096V on REFCOMP or driven with an external reference or DAC. If REFIN is tied low, the internal 2.5V reference divided by 2 (1.25V) is connected internally to the input of the reference buffer resulting in 2.048V on REFCOMP . If REFIN is tied high, the reference buffer is disabled and REFCOMP can be tied to REFOUT to achieve a 2.5V span or driven with an external reference or DAC. Table 3 summarizes the Reference modes.
Table 3. Reference Mode Table
MODE REFIN Tied Low REFIN is Buffer Input REFIN Tied High REFIN 0V Input 1v to 2.6 Input 5V Input REFCOMP 2.048V Output 1.6384V to 4.26V Output (1.6384 * REFIN) Input, 19.2k to Ground
Full Scale and Offset In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero during a calibration sequence. Offset error must be adjusted before full-scale error. Zero offset is achieved by adjusting the offset applied to the "-" input. For single-ended inputs, this offset should be applied to the COM pin. For differential inputs, the "-" input is dictated by the MUX address. For zero offset error, apply 0.5LSB (actual voltage will vary with input span selected) to the "+" input and adjust the offset at the "-" input until the output code flickers between 0000 0000 0000 and 0000 0000 0001 for the LTC1853 and between 00 0000 0000 and 00 0000 0001 for the LTC1852. As mentioned earlier, the internal reference is factory trimmed to 2.500V. To make sure that the reference buffer gain is not compensating for trim errors in the reference, REFCOMP is trimmed to 4.096V with an extremely accurate external 2.5V reference applied to REFIN. Likewise, to make sure that the full-scale gain trim is not compensating for errors in the reference buffer gain, the input full-scale gain is trimmed with an extremely accurate 4.096V reference applied to REFCOMP (REFIN = 5V to disable the reference buffer). This allows the use of either a 2.5V reference applied to REFIN or a 4.096V reference applied to REFCOMP to achieve accurate results. Full-scale errors can be trimmed to zero by adjusting the appropriate reference voltage. For unipolar inputs, an input voltage of FS - 1.5LSBs should be applied to the "+" input and the appropriate reference
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LTC1852/LTC1853 APPLICATIONS INFORMATION
adjusted until the output code flickers between 1111 1111 1110 and 1111 1111 1111 for the LTC1853 and between 11 1111 1110 and 11 1111 1111 for the LTC1852. For bipolar inputs, an input voltage of FS - 1.5LSBs should be applied to the "+" input and the appropriate reference adjusted until the output code flickers between 0111 1111 1110 and 0111 1111 1111 for the LTC1853 and between 01 1111 1110 and 01 1111 1111 for the LTC1852. These adjustments as well as the factory trims affect all channels. The channel-to-channel offset and gain error matching are guaranteed by design to meet the specifications in the Converter Characteristics table. OUTPUT DATA FORMAT The LTC1852/LTC1853 have a 14 bit/16-bit parallel output. The output word normally consists of a 10-bit/12-bit conversion result data word and a 4-bit address (three address bits A2OUT, A1OUT, A0OUT and the DIFFOUT bit). The output drivers are enabled when RD is low provided the chip is selected (CS is low). All 14/16 data output pins and BUSY are supplied by OVDD and OGND to allow easy interface to 3V or 5V digital logic. The data format of the conversion result is automatically selected and determined by the UNI/BIP input pin. If the UNI/BIP pin is low indicating a unipolar input span (0 - REFCOMP assuming PGA = 1), the format for the data is straight binary with 1 LSB = FS/4096 (1mV for REFCOMP = 4.096V). For the LTC1853 and 1LSB = FS/1024 (4mV for REFCOMP = 4.096V) for the LTC1852. If the UNI/BIP pin is high indicating a bipolar input span ( REFCOMP/2 for PGA = 1), the format for the data is two's complement binary with 1 LSB = [(+FS) - (-FS)]/4096 (1mV for REFCOMP = 4.096V). For the LTC1853 and 1LSB = [(+FS) - (-FS)]/1024 (4mV for REFCOMP = 4.096V) for the LTC1852. In both cases, the code transitions occur midway between successive integer LSB values (i.e., -FS + 0.5LSB, -FS + 1.5LSB, ... -1.5LSB, -0.5LSB, 0.5LSB, 1.5LSB, ... FS - 1.5LSB, FS - 0.5LSB). The three most significant bits of the data word (D11, D10 and D9 for the LTC1853; D9, D8 and D7 for the LTC1852)
OUTPUT CODE
also function as output bits when reading the contents of the programmable sequencer. During readback, a 7-bit status word (S6-S0) containing the contents of the current sequencer location is available when RD is low. The individual bits of the status word are outlined in Figure 1. During readback, the D8 to D0 pins (LTC1853) or D6 to D0 pins (LTC1852) remain high impedance irrespective of the state of RD.
Unipolar Transfer Characteristic (UNI/BIP = 0)
1111...1111 1111...1110 1111...1101 1000...0001 1000...0000 0111...1111 0111...1110 0000...0010 0000...0001 0000...0000 0 INPUT VOLTAGE (V) FS = VREFCOMP FS - 1LBS
18523 F01A
Bipolar Transfer Characteristic (UNI/BIP = 1)
0111...1111 0111...1110 0111...1101 BIPOLAR ZERO
OUTPUT CODE
0000...0001 0000...0000 1111...1111 1111...1110 1000...0010 1000...0001 1000...0000 -FS V FS = REFCOMP 2 -1LBS 0 1LBS INPUT VOLTAGE (V) FS - 1LBS
18523 F01B
S6
S5
S4
S3
S2
S1
S0
A1 A2 A0 MUX ADDRESS SINGLE-ENDED/ DIFFERENTIAL BIT
PGA BIT
END OF UNIPOLAR/ BIPOLAR BIT SEQUENCE BIT
18523 F01
Figure 1. Readback Status Word
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LTC1852/LTC1853 APPLICATIONS INFORMATION
BOARD LAYOUT AND BYPASSING To obtain the best performance from the LTC1852/LTC1853, a printed circuit board with ground plane is required. The ground plane under the ADC area should be as free of breaks and holes as possible, such that a low impedance path between all ADC grounds and all ADC decoupling capacitors is provided. It is critical to prevent digital noise from being coupled to the analog inputs, reference or analog power supply lines. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. An analog ground plane separate from the logic system ground should be established under and around the ADC. Pin 34 (OGND), Pin 13 (GND), Pin 16 (GND) and all other analog grounds should be connected to this single analog ground point. The bypass capacitors should also be connected to this analog ground plane. No other digital grounds should be connected to this analog ground plane. In some applications, it may be desirable to connect the OVDD to the logic system supply and OGND to the logic system ground. In these cases, OVDD should be bypassed to OGND instead of the analog ground plane. Low impedance analog and digital power supply common returns are essential to the low noise operation of the ADC and the foil width for these tracks should be as wide as possible. In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the sucessive approximation comparator. The problem can be eliminated by forcing the microprocessor into a WAIT state during conversions or by using three-state buffers to isolate the ADC bus. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC1852/LTC1853 have differential inputs to minimize noise coupling. Common mode noise on the "+" and "-" inputs will be rejected by the input CMRR. The LTC1852/LTC1853 will hold and convert the difference between whichever input is selected as the "+" input and whichever input is selected as the "-" input. Leads to the inputs should be kept as short as possible. SUPPLY BYPASSING High quality, low series resistance ceramic 10F bypass capacitors should be used. Surface mount ceramic capacitors such as Murata GRM235Y5V106Z016 provide excellent bypassing in a small board space. Alternatively, 10F tantalum capacitors in parallel with 0.1F ceramic capacitors can be used. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. DIGITAL INTERFACE Internal Clock The A/D converter has an internal clock that eliminates the need of synchronization between the external clock and the CS and RD signals found in other ADCs. The internal clock is factory trimmed to achieve a typical conversion time of 1400ns, and a maximum conversion time over the full operating temperature range of 2s. No external adjustments are required. The guaranteed maximum acquisition time is 150ns. In addition, a throughput time of 2.5s and a minimum sampling rate of 400ksps is guaranteed.
CS t3 SHDN
18523 F02
Figure 2. CS to SHDN Setup Timing
SHDN t4 CONVST
18523 F03
Figure 3. SHDN to CONVST Wake-Up Timing
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LTC1852/LTC1853 APPLICATIONS INFORMATION
CS t2 CONVST t1 RD
18523 F04
Figure 4. CS to CONVST and RD Setup Timing
the ADC has been selected (i.e., CS is low). Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output. BUSY is low during a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For the best results, ensure that CONVST returns high either within 400ns after the start of the conversion or after BUSY rises. Figures 5 through 9 show several different modes of operation. In modes 1a and 1b (Figures 5 and 6), CS and RD are both tied low. The falling edge of CONVST starts the conversion. The data outputs are always enabled and data can be latched with the BUSY rising edge. Mode 1a shows operation with a narrow logic low CONVST pulse. Mode 1b shows a narrow logic high CONVST pulse. In mode 2 (Figure 7), CS is tied low. The falling edge of CONVST signal again starts the conversion. Data outputs are in three-state until read by the MPU with the RD signal. Mode 2 can be used for operation with a shared MPU databus. In slow memory and ROM modes (Figures 8 and 9),CS is tied low and CONVST and RD are tied together. The MPU starts the conversion and reads the output with the RD signal. Conversions are started by the MPU or DSP (no external sample clock). In slow memory mode, the processor applies a logic low to RD ( = CONVST), starting the conversion. BUSY goes low, forcing the processor into a Wait state. The previous conversion result appears on the data outputs. When the conversion is complete, the new conversion results
Power Shutdown The LTC1852/LTC1853 provide two power shutdown modes, Nap and Sleep, to save power during inactive periods. The Nap mode reduces the power to 2.5mW and leaves only the digital logic and reference powered up. The wake-up time from Nap to active is 200ns. In Sleep mode, all bias currents are shut down and only leakage current remains--about 20A. Wake-up time from sleep mode is much slower since the reference circuit must power-up and settle to 0.005% for full 12-bit accuracy (0.02% for full 10-bit accuracy). Sleep mode wake-up time is dependent on the value of the capacitor connected to the REFCOMP (Pin 12). The wake-up time is 10ms with the recommended 10F capacitor. Shutdown is controlled by Pin 47 (SHDN); the ADC is in shutdown when it is low. The shutdown mode is selected with Pin 46 (CS); low selects Nap (Figures 2 and 3). Timing and Control Conversion start and data read operations are controlled by three digital inputs: CONVST, CS and RD (Figure 4). A logic "0" applied to the CONVST pin will start a conversion after
tCONV t5 CONVST t6 BUSY t7 DATA DATA (N - 1)
t8
DATA N
18523 F05
Figure 5. Mode 1a CONVST Starts a Conversion. Data Outputs Always Enabled (CS = RD = 0)
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LTC1852/LTC1853 APPLICATIONS INFORMATION
t13 CONVST t6 BUSY t7 DATA DATA (N - 1) DATA N
18523 F06
tCONV t5
t8
t6
Figure 6. Mode 1b CONVST Starts a Conversion, RD = CS = 0
tCONV t5 CONVST t6 BUSY t9 RD t10 DATA DATA N
18523 F07
t8
t13
t12
t11
Figure 7. Mode 2 CONVST Starts a Conversion. Data is Read by RD, CS = 0
tCONV RD = CONVST t6 BUSY t10 DATA DATA (N - 1) t7 DATA N DATA N DATA (N + 1)
18523 F08
t8
t11
Figure 8. Slow Memory Mode Timing, CS = 0
tCONV CONVST t6 BUSY t10 DATA DATA (N - 1) DATA N
18523 F09
t8
t11
Figure 9. ROM Mode Timing, CS = 0
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LTC1852/LTC1853 APPLICATIONS INFORMATION
appear on the data outputs; BUSY goes high releasing the processor, and the processor takes RD ( = CONVST) back high and reads the new conversion data. In ROM mode, the processor takes RD ( = CONVST) low, starting a conversion and reading the previous conversion result. After the conversion is complete, the processor can read the new result and initiate another conversion. MODES OF OPERATION Direct Address Mode The simplest mode of operation is the Direct Address mode. This mode is selected when both the M1 and M0 pins are low. In this mode, the address input pins directly control the MUX and the configuration input pins directly control the input span. The address and configuration input pins are enabled when WR is low. WR can be tied low if the pins will be constantly driven or the rising edge of WR can be used to latch and hold the inputs for as long as WR is held high. Scan Mode Scan mode is selected when M1 is low and M0 is high. This mode allows the converter to scan through all of the input channels sequentially and repeatedly without the user having to provide an address. The address input pins (A2 to A0) are ignored but the DIFF PGA and , UNI/BIP pins are still enabled when WR is low. As in the direct address mode, WR can be held low or the rising edge of WR can be used to latch and hold the information on these pins for as long as WR is held high. The DIFF pin selects the scan pattern. If DIFF is held low, the scan pattern will consist of all eight channels in succession, single-ended relative to COM (CH0-COM, CH1-COM, CH2-COM, CH3-COM, CH4-COM, CH5-COM, CH6-COM, CH7-COM, repeat). At the maximum conversion rate the throughput rate for each channel would be 400ksps/8 or 50ksps. If DIFF is held high, the scan pattern will consist of four differential pairs (CH0-CH1, CH2-CH3, CH4-CH5, CH6-CH7, repeat). At the maximum conversion rate, the throughput rate for each pair would be 400ksps/4 or 100ksps. It is possible to drive the DIFF input pin while the part is in Scan mode to achieve combinations of single-ended and differential inputs. For instance, if the A0OUT pin is tied to the DIFF input pin, the scan pattern will consist of four single-ended inputs and two differential pairs (CH0-COM single-ended, CH1-COM single-ended, CH2-CH3 differential, CH4-COM single-ended, CH5-COM single-ended, CH6-CH7 differential, repeat). The scan counter is reset to zero whenever the M0 pin changes state so that the first conversion after M0 rises will be MUX Address 000 (CH0-COM single-ended or CH0CH1 differential depending on the state of the DIFF pin). A conversion is initiated by the falling edge of CONVST. After each conversion, the address counter is advanced (by one if DIFF is low, by two if DIFF is high) and the MUX address for the present conversion is available on the address output pins (DIFFOUT, A2OUT to A0OUT) along with the conversion result. Program/Readback Mode The LTC1852 and LTC1853 include a sequencer that can be programmed to run a sequence of up to 16 locations containing a MUX address and input configuration. The MUX address and input configuration for each location are programmed using the DIFF A2 to A0, UNI/BIP and , PGA pins and are stored in memory along with an end-ofsequence (EOS) bit that is generated automatically. The six input address and configuration bits plus the EOS bit can be read back by accessing the 7-bit readback status word (S6-S0) through the data output pins. The sequencer memory is a 16 x 7 block of memory represented by the block diagram in Figure 10.
DIFF LOCATION 0000 A2 A1 A0 UNI/BIP PGA EOS
LOCATION 0001
LOCATION 0010 * * * LOCATION 1110 * * * * * * * * * * * * * * * * * *
LOCATION 1111
18523 F10
Figure 10. Sequencer Memory Block Diagram
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LTC1852/LTC1853 APPLICATIONS INFORMATION
The sequencer is accessed by taking the M1 mode pin high. With M1 high, the sequencer memory is accessed by taking the M0 mode pin low. This will cause BUSY to go low, disabling conversions during the programming and readback of the sequencer. The sequencer is reset to location 0000 whenever M1 or M0 changes state. One of these signals should be cycled prior to any read or write operation to guarantee that the sequencer will be programmed or read starting at location 0000. The sequencer is programmed sequentially starting from location 0000. RD and WR should be held high, the appropriate signals applied to the DIFF pin, the A2 to A0 MUX address pins, the UNI/BIP pin and the PGA pin and WR taken low to write to the memory. WR going high will latch the data into memory and advance the pointer to the next sequencer location. Up to 16 locations can be programmed and the last location written before M0 is taken back high will be the last location in the sequence. After 16 writes, the pointer is reset to location 0000 and any subsequent writes will erase all of the previous contents and start a new sequence. The sequencer memory can be read by holding WR high and strobing RD. Taking RD low accesses the sequencer memory and enables the data output pins. The sequencer should be reset to location 0000 before beginning a read operation (by applying a positive pulse to MO). The seven output bits will be available on the DIFFOUT/S6, A2OUT/S5, A1OUT/S4, A0OUT/S3, D11/S2, D10/S1 and D9/S0 pins (LTC1853) or DIFFOUT/S6, A2OUT/S5, A1OUT/S4, A0OUT/S3, D9/S2, D8/S1 and D7/S0 pins (LTC1852). The D8 to D0 (LTC1853) or D6 to D0 (LTC1852) data output pins will remain high impedance during readback. RD going high will return the data output pins to a high impedance state
Table 5
OPERATION MODE Direct Address Scan Program Readback Sequence Run M1 0 0 0 0 1 1 1 M0 0 0 1 1 0 0 1 1 X OE WR 0 0 RD OE OE OE OE 1 COMMENTS Address and Configuration are Driven from External Pins Address and Configuration are Latched on Rising Edge of WR or Falling Edge of CONVST Address is Provided by Internal Scan Counter, Configuration is Driven from External Pins Configuraton is Latched on Rising Edge of WR or Falling Edge of CONVST Write Sequencer Location, WR Low Enables Inputs, Rising Edge of WR Latches Data and Advances to Next Location Read Sequencer Location, Falling Edge of RD Enables Output, Rising Edge of RD Advances to Next Location Run Programmed Sequence, Falling Edge of CONVST Starts Conversion and Advances to Next Location
18523fa
and advance the pointer to the next location. A logic 1 on the D9/S0 (D7/S0) pin indicates the last location in the current sequence but all 16 locations can be read by continuing to clock RD. After 16 reads, the pointer is reset to location 0000. When all programming and/or reading of the sequencer memory is complete, M0 is taken high. BUSY will come back high enabling CONVST and indicating that the part is ready to start a conversion. Sequence Run Mode Once the sequencer is programmed, M0 is taken high. BUSY will also come back high enabling CONVST and the next falling CONVST will begin a conversion using the MUX address and input configuration stored in location 0000 of the sequencer memory. After each conversion, the sequencer pointer is advanced by one and the MUX address ( the actual channel or channels being converted, not the sequencer pointer) for the present conversion is available on the address output pins along with the conversion result. When the sequencer finishes converting the last programmed location, the sequencer pointer will return to location 0000 for the next conversion. The sequencer will also reset to location 0000 anytime the M1 or M0 pin changes state. The contents of the sequencer memory will be retained as long as power is contiuously applied to the part. This allows the user to switch from Sequence Run mode to either Direct Address or Scan Mode and back without losing the programmed sequence. The part can also be disabled using CS or shutdown in Nap or Sleep mode without losing the programmed sequence. Table 5 outlines the operational modes of the LTC1852/LTC1853. Figures 11 and 12 show the timing diagrams for writing to, reading from and running a sequence.
19
LTC1852/LTC1853
20
t18 t23 t23 t17 t15 t16 t24 t12 t14
M1
M0
CONVST
WR
t20
RD t22 L0CATION 0000 L0CATION 0001 L0CATION n
APPLICATIONS INFORMATION
DIFF
A2 TO A0
L0CATION 0000
L0CATION 0001
L0CATION n
UNI/BIP L0CATION 0000 L0CATION 0001 L0CATION n
PGA t19
L0CATION 0000
L0CATION 0001
L0CATION n
BUSY t11
LOCATION 0000
t10
LOCATION 0001 LOCATION n LOCATION n+1
Hi-Z
S6 TO S0
Hi-Z
18523 F11
D6 TO D0 (LTC1852) D8 TO D0 (LTC1853)
Figure 11. Sequencer I/O
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M1 t18
M0 CONVERT 0000 CONVERT 0001 CONVERT 0010 CONVERT 0000
CONVST t20 t17 t25 t8 t5
WR t16 t15 t14 t23
APPLICATIONS INFORMATION
RD
DIFF
L0CATION 0000
L0CATION 0001
L0CATION 0010
A2 TO A0
L0CATION 0000 L0CATION 0010
L0CATION 0001
UNI/BIP L0CATION 0000 L0CATION 0010 L0CATION 0001
PGA t19 t6
L0CATION 0000
L0CATION 0001
L0CATION 0010
BUSY t7
DATA 0000 DATA 0001
t11
t10
DATA 0010 DATA 0000
18523 F12
DIFFOUT A2OUT TO A0OUT D9 TO D0 (LTC1852) D11 TO D0 (LTC1853)
Hi-Z
Figure 12. Programming and Running a Sequence
LTC1852/LTC1853
21
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LTC1852/LTC1853 TYPICAL APPLICATIONS
LTC1853 Hardwired for 8-Channel Single-Ended Scan with Unipolar 0V to 4.096V Operation
5V 10F 14 VDD 15 VDD LTC1853 M1 48 M0 36 SHDN 47 CS 46 CONVST 45 CONTROL LOGIC AND PROGRAMMABLE SEQUENCER RD 44 WR 43 DIFF 42 A2 41 A1 40 8-CHANNEL MULTIPLEXER A0 39 INTERNAL CLOCK UNI/BIP 38 PGA 37 OVDD 35 7 CH6 8 CH7 9 COM BUSY 33 DIFFOUT/S6 17 A2OUT/S5 18 A1OUT/S4 19 A0OUT/S3 20 2.5V 1F 10 REFOUT 2.5V REFERENCE D11/S2 21 5V 2.7V TO VDD 10F 0.1F CONVERT CLOCK 5V 5V 0.1F
1 CH0 2 CH1 3 CH2 INPUT CONFIGURATION: ALL 8 CHANNELS SINGLE ENDED TO COM CH0-CH7: 0V TO 4.096V 4 CH3 5 CH4 6 CH5
+ -
12-BIT SAMPLING ADC
DATA LATCHES
OUTPUT DRIVERS
D10/S1 22 D9/S0 23 D8 24 D7 25
11 REFIN
REF AMP 1.6384X
D6 26 D5 27 D4 28 D3 29 D2 30 D1 31 D0 32 OGND 34
18523 TA01
4.096V 0.1F 10F
12 REFCOMP
GND 13
GND 16
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22
LTC1852/LTC1853 TYPICAL APPLICATIONS
LTC1853 Hardwired for 4-Channel Differential Scan with Bipolar 1.024V Operation
5V 10F 14 VDD 15 VDD LTC1853 M1 48 M0 36 SHDN 47 CS 46 CONVST 45 CONTROL LOGIC AND PROGRAMMABLE SEQUENCER RD 44 WR 43 DIFF 42 A2 41 A1 40 8-CHANNEL MULTIPLEXER A0 39 INTERNAL CLOCK UNI/BIP 38 PGA 37 OVDD 35 7 CH6 8 CH7 9 COM BUSY 33 DIFFOUT/S6 17 A2OUT/S5 18 A1OUT/S4 19 A0OUT/S3 20 2.5V 1F 10 REFOUT 2.5V REFERENCE D11/S2 21 10F 5V 3V TO 5V 0.1F CONVERT CLOCK 5V 5V 5V 0.1F
+ - +
INPUT CONFIGURATION: 4 DIFFERENTIAL CHANNELS: 1.024V
1 CH0 2 CH1 3 CH2 4 CH3 5 CH4 6 CH5
- + - + -
+ -
12-BIT SAMPLING ADC
DATA LATCHES
OUTPUT DRIVERS
D10/S1 22 D9/S0 23 D8 24 D7 25
11 REFIN
REF AMP 1.6384X
D6 26 D5 27 D4 28 D3 29 D2 30 D1 31 D0 32 OGND 34
18523 TA02
4.096V 0.1F 10F
12 REFCOMP
GND 13
GND 16
PACKAGE DESCRIPTION
48 25
FW Package 48-Lead Plastic TSSOP (6.1mm)
(Reference LTC DWG # 05-08-1651 Rev A)
0.95 0.10 12.40 - 12.60* (.488 - .496) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
8.4 0.10
6.2 0.10 7.9 - 8.3 (.311 - .327)
1 0.32 0.05
24 0.50 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1.10 (.0433) MAX
RECOMMENDED SOLDER PAD LAYOUT 6.0 - 6.2** (.236 - .244)
0.25 REF 0 - 8 NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES)
-C0.50 (.0197) BSC 0.17 - 0.27 (.0067 - .0106) TYP 0.05 - 0.15 (.002 - .006)
-T0.10 C
FW48 TSSOP REV A 1005
0.09 - 0.20 0.45 - 0.75 (.0035 - .008) (.018 - .029) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC1852/LTC1853 TYPICAL APPLICATION
Data buffering using two IDT7202LA15 1k x 9-bit FIFOs allows rapid collection of 1024 samples and simple interface to low power, low speed, 8-bit microcontrollers. Data and channel information are clocked in simultaneously and read out as two bytes using READ HIGH FIFO and READ LOW FIFO lines. In the event of bus contention, resistors limit peak output current. If both FIFOs are read completely or
INPUT CONFIGURATION: ALL 8 CHANNELS SINGLE ENDED TO COM CH0-CH7: 0V TO 4.096V 5V 5V 10F 14 15 VDD LTC1853 0.1F OVDD 35 M1 48 M0 36 SHDN 47 CS 46 CONVST 45 CONTROL LOGIC AND PROGRAMMABLE SEQUENCER RD 44 WR 43 DIFF 42 A2 41 A1 40 8-CHANNEL MULTIPLEXER A0 39 INTERNAL CLOCK UNI/BIP 38 PGA 37 BUSY 33 DIFFOUT/S6 17 A2OUT/S5 18 A1OUT/S4 19 A0OUT/S3 20 2.5V 10 REFOUT 2.5V REFERENCE D11/S2 21 HIGH_FIFO_FULL_FLAG LOW_FIFO_FULL_FLAG FIFO_RESET 0.1F 5V 2 24 25 26 27 3 4 5 6 1 8 22 *CONVERT CLOCK UP TO 1024 28 IDT7202LA15 13 D8 Q8 19 D7 Q7 18 D6 Q6 17 D5 Q5 16 D4 Q4 12 D3 Q3 11 D2 Q2 10 D1 Q1 9 D0 Q0 15 WR R 21 FF EF 20 RS HF 23 RT GND XI 7 14 8 x 1k 5V 5V 5V 10F 0.1F 2 24 25 26 27 3 4 5 6 1 8 22
reset before a burst of conversions, the empty, half full, and full flags from only one FIFO need to be monitored. The retransmit inputs may also be tied together. Retransmit may be used to read data repeatedly, allowing a memory limited processor to perform transform and filtering functions that would otherwise be difficult.
0.1F 5V 28 IDT7202LA15 13 D8 Q8 8 x 1k 18 D7 Q7 18 D6 Q6 17 D5 Q5 16 D4 Q4 12 D3 Q3 11 D2 Q2 10 D1 Q1 9 D0 Q0 15 WR R READ_HIGH_FIFO 21 FF EF HIGH_FIFO_EMPTY 20 RS HF HIGH_FIFO_HALF_FULL 23 RT HIGH BYTE_FIFO_RETRANSMIT GND XI 7 14
VDD
8-BIT DATA BUS D7 D6 D5 D4 D3 D2 D1 D0
1 CH0 2 CH1 3 CH2 4 CH3 5 CH4 6 CH5 7 CH6 8 CH7 9 COM
+ -
12-BIT SAMPLING ADC
DATA LATCHES
OUTPUT DRIVERS
D10/S1 22 D9/S0 23 D8 24 D7 25
11 REFIN 1F
REF AMP 1.6384X
D6 26 D5 27 D4 28 D3 29 D2 30 D1 31 D0 32 REFCOMP 12 GND 13 GND 16 OGND 34
READ_LOW_FIFO LOW_FIFO_EMPTY LOW_FIFO_HALF_FULL LOW BYTE_FIFO_RETRANSMIT
4.096V 0.1F 10F
18523 TA03
RELATED PARTS
PART NUMBER LTC1410 LTC1415 LTC1418 LTC1419 LTC1604 LTC1850/LTC1851 DESCRIPTION 12-Bit, 1.25Msps, 5V ADC 12-Bit, 1.25Msps, Single 5V ADC 14-Bit, 200ksps, Single 5V ADC Low Power 14-Bit, 800ksps ADC 16-Bit, 333ksps, 5V ADC 10-Bit/12, 8-Channel, 1.25Msps ADCs COMMENTS 71.5dB SINAD at Nyquist, 150mW Dissipation 55mW Power Dissipation, 72dB SINAD 15mW, Serial/Parallel 10V True 14-Bit Linearity, 81.5dB SINAD, 150mW Dissipation 90dB SINAD, 220mW Power Dissipation, Pin Compatible with LTC1608 Pin-Compatible, Programmable Multiplexer and Sequencer
18523fa LT 0108 REV A * PRINTED IN USA
24 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2001

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